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An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes
2004
Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage scaling in each on-chip cores individually, many on-chip voltage regulators must be used. However, the limitations in implementation of onchip inductors can reduce the efficiency, accuracy and the number of voltage modes generated by regulators. Therefore the future voltage scheduling algorithms must be efficient, even
doi:10.1145/1013235.1013326
dblp:conf/islped/GorjiaraBC04
fatcat:lglgd6axrzhojm6rwatdr6o2ka