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Empirical CPU power modelling and estimation in the gem5 simulator
2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Power modelling is important for modern CPUs to inform power management approaches and allow design space exploration. Power simulators, combined with a full-system architectural simulator such as gem5, enable power-performance trade-offs to be investigated early in the design of a system with different configurations (e.g number of cores, cache size, etc.). However, the accuracy of existing power simulators, such as McPAT, is known to be low due to the abstraction and specification errors, anddoi:10.1109/patmos.2017.8106988 dblp:conf/patmos/ReddyWBDAM17 fatcat:ohddtkh4rzeh7dlqrdn22miryy