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Exploiting Nested Parallelism on Heterogeneous Processors
2016
Heterogeneous computing systems have become common in modern processor architectures. These systems, such as those released by AMD, Intel, and Nvidia, include both CPU and GPU cores on a single die available with reduced communication overhead compared to their discrete predecessors. Currently, discrete CPU/GPU systems are limited, requiring larger, regular, highly-parallel workloads to overcome the communication costs of the system. Without the traditional communication delay assumed between
doi:10.13016/m28b6v
fatcat:j7ujskmmnbgzvnvahjjrbo3vkq