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The last few years have witnessed high-end processors with increasing number of cores and increasingly larger dies. Limited instruction-level parallelism (ILP), chip power constraints and technology scaling limitations caused designers to embrace multiple cores rather than single-core performance scaling to improve chip throughput. In this paper we try to answer whether that approach is sustainable by scaling from a state-of-theart big chip design point using analytical models. We consider adoi:10.1109/mm.2011.42 fatcat:6ard3cb27zhi3c6prnkunieiqy