Scaling with Design Constraints: Predicting the Future of Big Chips

Wei Huang, Karthick Rajamani, Mircea R. Stan, Kevin Skadron
2011 IEEE Micro  
The last few years have witnessed high-end processors with increasing number of cores and increasingly larger dies. Limited instruction-level parallelism (ILP), chip power constraints and technology scaling limitations caused designers to embrace multiple cores rather than single-core performance scaling to improve chip throughput. In this paper we try to answer whether that approach is sustainable by scaling from a state-of-theart big chip design point using analytical models. We consider a
more » ... prehensive set of design constraints/trends including core growth rate, cache size, voltage-frequency scaling, thermal design power (TDP), hot spots and die area. We conclude that 1) Even at constatn frequency, a 2X per generation core growth will exceed TDP soon. 2) Scaling chip throughput will be difficult at constant TDP. Voltage scaling techniques, such as near-threshold operation, will be a key determinant on the extent of dark-vs-dim silicon when maximizing chip throughput. 3) Within two technology generations, the gap between technology-scaling-promised throughput and TDP-constrained throughput would need new architectural innovations to be bridged. 4) Even if relaxing strict TDP/area con straints, system power constraints might force the adoption of new packaging (3D, SiP) solutions to realize throughput growth. Then new thermal issues will be the hurdle, necessitating the adoption of better cooling solutions. * Wei Huang and Karthick Rajamani are with IBM Research -Austin. † Micea R. Stan is with the Charles L.
doi:10.1109/mm.2011.42 fatcat:6ard3cb27zhi3c6prnkunieiqy