A novel sequential circuit optimization with clock gating logic

Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang
2008 2008 IEEE/ACM International Conference on Computer-Aided Design  
To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the clock-gating conditions and the next-state function of a Flip-Flop (FF) are correlated and can be used for sequential optimization. We show that the implementation of the next-state function of any FF can be just an inverter if the clock signal is appropriately gated. By exploiting the flexibility between the clock-gating
more » ... the clock-gating conditions and the nextstate function, we propose an iterative optimization technique to minimize the overall timing.
doi:10.1109/iccad.2008.4681579 dblp:conf/iccad/KuoWC08 fatcat:xptp4v5ao5anlmpx7bk2gdsyze