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Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure
2014
International Journal of Computer Science & Information Technology (IJCSIT)
Simulation times of complex System-on-Chips (SoC) have grown exponentially as designs reach the multi-million ASIC gate range. Verification teams have adopted emulation as a prominent methodology, incorporating high-level testbenches and FPGA/ASIC hardware for system-level testing (SLT). In addition to SLT, emulation enables software teams to incorporate software applications with cycle-accurate hardware early on in the design cycle. The Standard for Co-Emulation Modeling Interface (SCE-MI)
doi:10.5121/ijcsit.2014.6406
fatcat:ryxoy6fasfax3nsvrbnxca6e4e