Flexible auto-refresh

Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce Jacob
2015 Proceedings of the 42nd Annual International Symposium on Computer Architecture - ISCA '15  
Capacitive DRAM cells require periodic refreshing to preserve data integrity. In JEDEC DDRx devices, a refresh operation is carried out via an auto-refresh command, which refreshes multiple rows from multiple banks simultaneously. The internal implementation of auto-refresh is completely opaque outside the DRAM-all the memory controller can do is to instruct the DRAM to refresh itselfthe DRAM handles all else, in particular determining which rows in which banks are to be refreshed. This is in
more » ... nflict with a large body of research on reducing the refresh overhead, in which the memory controller needs fine-grained control over which regions of the memory are refreshed. For example, prior works exploit the fact that a subset of DRAM rows can be refreshed at a slower rate than other rows due to access rate or retention period variations. However, such row-granularity approaches cannot use the standard auto-refresh command, which refreshes an entire batch of rows at once and does not permit skipping of rows. Consequently, prior schemes are forced to use explicit sequences of activate (ACT) and precharge (PRE) operations to mimic row-level refreshing. The drawback is that, compared to using JEDEC's autorefresh mechanism, using explicit ACT and PRE commands is inefficient, both in terms of performance and power. In this paper, we show that even when skipping a high percentage of refresh operations, existing row-granurality refresh techniques are mostly ineffective due to the inherent efficiency disparity between ACT/PRE and the JEDEC autorefresh mechanism. We propose a modification to the DRAM that extends its existing control-register access protocol to include the DRAM's internal refresh counter. We also introduce a new "dummy refresh" command that skips refresh operations and simply increments the internal counter. We show that these modifications allow a memory controller to reduce as many refreshes as in prior work,
doi:10.1145/2749469.2750408 dblp:conf/isca/BhatiCLJ15 fatcat:4fy7jmmcnffwphnn4yszpbuiaa