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Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due to capacity and compulsory misses. Trace preconstruction augments a trace cache by performing a function analogous to prefetching. The trace preconstruction mechanism observes the processor's instruction dispatch stream to detect opportunities for jumping ahead of the processor. After doing so, the preconstructiondoi:10.1145/339647.339653 fatcat:zmo6qxkldbdpfpgp7bhqms4sui