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Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes
2019
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
We present Golden Gate, an FPGA-based simulation tool that decouples the timing of an FPGA host platform from that of the target RTL design. In contrast to previous work in static time-multiplexing of FPGA resources, Golden Gate employs the Latency-Insensitive Bounded Dataflow Network (LI-BDN) formalism to decompose the simulator into subcomponents, each of which may be independently and automatically optimized. This structure allows Golden Gate to support a broad class of optimizations that
doi:10.1109/iccad45719.2019.8942087
dblp:conf/iccad/MagyarBKSBA19
fatcat:4xjzrmr245bjtj5hcbexq2fhue