Industrial implementations of DSP systems today require extreme complexity. Examples are wireless systems satisfying standards like WLAN or 3GPP, video components, or multimedia players. At the same time, often harsh constraints like low-power requirements burden the designer even more. Conventional methods for ASIC design are not sufficient any more to guarantee a fast conversion from initial concept to final product. In industry, the problem has been addressed by the wording design crisis or

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... esign gap. While this design gap exists in a complexity gap, that is, a difference between existing, available, and demanded complexity, there is also a productivity gap, that is, the difference between available complexity and how much we are able to efficiently convert into gate-level representations. This special issue intends to present recent solutions to such gaps addressing algorithmic design methods, algorithms for floating-to-fixed-point conversion, automatic DSP coding strategies, architectural exploration methods, hardware/software partitioning, as well as virtual and rapid prototyping. We received 20 submissions from different fields and areas of expertise from which finally only 12 were accepted for publication. These 12 papers can be categorised into four groups: pure VLSI design methods, prototyping methods, experimental reports on FPGAs, and floating-to-fixed-point conversions. Most activities in design methods are related to the final product. VLSI design methods intend to deal with high complexity in a rather short time. In this special issue, we present five contributions allowing to design complex VLSI designs in substantially lower time periods. In "Macrocell builder: IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems", N.-E. Zergainoh et al. present a design tool, called DSP macrocell builder, that generates SystemC regis-ter transfer level architectures for VLSI signal processing systems from high-level representations as interconnections of intellectual property (IP) blocks. The development emphasizes extensive parameterization and component reuse to improve productivity and flexibility. Careful generation of control structures is also performed to manage delays and coordinate parallel execution. Effectiveness of the tool is demonstrated on a number of high-throughput signal processing applications. In "Multiple-clock cycle architecture for the VLSI design of a system for time-frequency analysis," Veselin N. Ivanović et al. present a streamlined architecture for time-frequency signal analysis. The architecture enables real-time analysis of a number of important time-frequency distributions. By providing for multiple-clock-cycle operation and resource sharing across the design in an efficient manner, the architecture achieves these features with relatively low hardware complexity. Results are given based on implementation of the architecture on field-programmable gate arrays, and a thorough comparison is given against a single-cycle implementation architecture. In "3D-SoftChip: a novel architecture for next-generation adaptive computing systems," C. Kim et al. present an architecture for real-time communication and signal processing through vertical integration of a configurable array processor subsystem and a switch subsystem. The proposed integration is achieved by means of an indium bump interconnection array to provide high interconnection bandwidth at relatively low levels of power dissipation. The paper motivates and develops the design of the proposed system architecture, along with its 2D subsystems and hierarchical interconnection network. Details on hardware/software codesign aspects of the proposed system are also discussed. In "Highly flexible multimode digital signal processing systems using adaptable components and controllers", V. V.