Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL,

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... NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate.