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Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL,doi:10.11648/j.jeee.20170506.15 fatcat:z4csd24gtzh55arj4wcjemesaq