Architectural and physical design challenges for one-million gate FPGAs and beyond

Jonathan Rose, Dwight Hill
1997 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97  
Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here, and larger devices shortly after that. We feel that current architectures will not extend directly to this scale because: they do not handle routing delays effectively; they require excessive compile/place/route times; and because they do not exploit new opportunities presented by the increase in available transistors and wiring. In this paper we describe several challenges that
more » ... will need to be solved for these large-scale FPGAs to realize their full potential. 1. Here we assume that one 4-input lookup table plus one D flip-flop are equivalent to 12 "gates.
doi:10.1145/258305.258324 dblp:conf/fpga/RoseH97 fatcat:middzs76z5bfvn36itskd3ct3u