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Improving worst-case cache performance through selective bypassing and register-indexed cache
2015
Proceedings of the 52nd Annual Design Automation Conference on - DAC '15
Worst-case execution time (WCET) analysis is a critical part of designing real-time systems that require strict timing guarantees. Data caches have traditionally been challenging to analyze in the context of WCET due to the unpredictability of memory access patterns. In this paper, we present a novel register-indexed cache structure that is designed to be amenable to static analysis. This is based on the idea that absolute addresses may not be known, but by using relative addresses, analysis
doi:10.1145/2744769.2744855
dblp:conf/dac/IsmailLS15
fatcat:y76moji7ojakpfygeov42o4umm