This paper presents design and simulation of switched resistor (SR) ∆∑ ADC in analog mixed signal (AMS) environment. The proposed design consists of 1 st order single bit SR ∆∑ modulator with dissipated power of 0.935mW and 2 nd order digital decimation filter. Such modulator offers high-performance due to small delay which is achieved by simple circuitry. SR technique is chosen to achieve reduction of element and components, low power dissipated in hardware realization, and ability of tunable.

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... The proposed decimation filter design consists of a second order Cascaded integrator Comb filter (CIC). Such structure no need multipliers in order to save silicon area. The proposed design and simulation are carried out using Mentor Graphics SystemVision tools. The switched resistor (SR) ADC offers resolution of 10-Bit using 64 Oversampling ratio.