In this letter, we report the heterogeneous integration of vertically aligned silicon (Si) microprobe arrays/(111) with MOSFET circuits/(100) by IC processes and subsequent selective vapor-liquid-solid (VLS) growth of Si. A hybrid Si-on-insulator (SOI) substrate with different species of Si layers, e.g., a (100)-top-Si/buried oxide/(111)-handle-Si system, was utilized for the heterogeneous integration technique. MOSFETs were fabricated on (100) top Si, and vertical VLS probes were synthesized

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... the selectively exposed (111) handle Si. The different Si layers of the MOSFETs and probes were electrically connected by a 3-D metallization technique. In addition, the electrical properties of 3-D metallization and the MOSFETs were investigated. The results indicate potential for heterogeneous integration of VLS probes/(111) and MOSFETs/(100), promising further integrations of numerous microdevices/different species of substrates and CMOS/(100), including fully depleted SOI-CMOS for high-performance electronics, on the same chip. Index Terms-Heterogeneous integration, MOSFETs, siliconon-insulator (SOI) substrate, vapor-liquid-solid (VLS) growth.