A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is
Variable-taper CMOS buffers
IEEE Journal of Solid-State Circuits
A variable-taper (VT) approach to buffer design is proposed where the taper from one inverter stage to the next is a function of the position of the inverter within the buffer chain. Though the minimum delay obtained by using a VT buffer is about 15~o more than the minimum delay obtained from conventional fixed-taper (ET) buffers, a small modification to the initial stages of the VT buffer reduces this difference to less than 2%. For similar delays, a VT buffer usually takes less area and consumes less power than an IT buffer.doi:10.1109/4.84943 fatcat:vpw6fa2wtbac5gj5zbjasnzihi