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Power consumption has become one of the biggest challenges in design of high performance microprocessors. In this paper we present a design technique using GALs (Globally-Asynchronous Locally-Synchronous) for implementing asynchronous ALUs, which aims to eliminate the global clock. Here ALUs are designed with delay insensitive dual rail four phase logic and CMOS domino logic. It ensures economy in silicon area and potentially for low power consumption. This has been described and implemented indoi:10.9790/2834-0360712 fatcat:qnziz43njfhgblnina7p2mm4dm