A power model for routers: modeling Alpha 21364 and InfiniBand routers

Hang-Sheng Wang, Li-Shiuan Peh, S. Malik
Proceedings 10th Symposium on High Performance Interconnects  
Interconnection networks, historically used to connect processors and memories in large multiprocessors, are becoming prevalent in many new applications. Designers have deployed interconnection networks to connect workstation clusters, 1 terabit Internet router line cards, 2 and server blades. 3 Recently, designers have used interconnection networks as the fabric for on-chip networks. 4 In many applications, a low-latency, highthroughput fabric no longer suffices. Designers must work within a
more » ... ust work within a tight power budget and make architectural-level decisions that consider power in addition to performance. Routers and links of an interconnection network already consume a significant portion of the overall system power. The integrated router and links of the Alpha 21364 microprocessor 5 consume about 20 percent of the total system power (25 W out of total chip power of 125 W), while the interconnection network circuitry on a router line card accounts for about 33 percent of the line card's total power consumptions. Designers of an InfiniBand-enabled server blade allocated roughly the same power budget to the router and the microprocessor. 3 With increasing demand for network bandwidth, the power that an interconnection network consumes will be even more substantial. Although researchers and designers have pretty well understood processing and memory elements' power consumption, 6 they have largely neglected that of network elements. This motivated us to develop an architectural-level power model for interconnection network routers, so researchers and designers can factor in power estimates easily when exploring different architectural tradeoffs. This power model is part of our effort to provide a complete network simulation platform where designers and researchers can pick, plug, and play different components to form myriad network architectures, run diverse communication workloads, and rapidly explore network power and performance alternatives. See sidebar on Orion. Related work Architectural-level power estimation is suitable for design space exploration because it is much faster than low-level power estimation
doi:10.1109/conect.2002.1039253 dblp:conf/hoti/WangPM02 fatcat:zgwk3papq5flvpxfldmlgzmhdq