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Speculation techniques for improving load related instruction scheduling
SIGARCH Computer Architecture News
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for dispatching instructions to execution units based on dependencies, latencies, and resource availability. Most existing instruction schedulers are doing a less than optimal job of scheduling memory accesses and instructions dependent on them, for the following reasons: • Memory dependencies cannot be resolved prior todoi:10.1145/307338.300983 fatcat:7i4xqvayhzdfbimg7b7ez6vjum