Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

Chin-Hsin Lin, Marek Syrzycki
2011 Circuits and Systems  
This paper presents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13 μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6 ns with a time resolution of 25 ps.
doi:10.4236/cs.2011.24050 fatcat:7s3rhefjzjg6dgklulphx35j6e