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DAG-aware logic synthesis of datapaths
2016
Proceedings of the 53rd Annual Design Automation Conference on - DAC '16
Traditional datapath synthesis for standardcell designs go through extraction of arithmetic operations from the high-level description, high-level synthesis, and netlist generation. In this paper, we take a fresh look at applying high-level synthesis methodologies in logic synthesis. We present a DAG-Aware synthesis technique for datapaths synthesis which is implemented using And-Inv-Graphs. Our approach targets area minimization. The proposed algorithm includes identifying vector multiplexers,
doi:10.1145/2897937.2898000
dblp:conf/dac/YuCCS16
fatcat:y7bu5hvllfcgji2z5ofznjq4uy