Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. Instead of trying to manufacture defect-free chips in which transient errors are assumed to be uncommon, future processor architectures must be designed to adapt to, and coexist with, substantial numbers of manufacturing defects and high transient error rates. We introduce the Recursive NanoBox Processor Grid as

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... an application specific, fault-tolerant, parallel computing system designed for fabrication with unreliable nanotechnology devices. This architecture is composed of many simple processor cells connected together in a two dimensional grid. It uses a recursive black box architecture approach to isolate and mask these transient faults and defects. In this initial study we construct VHDL models of one processor cell and evaluate the effectiveness of our recursive fault masking approach in the presence of random transient errors. Our analysis shows that this architecture can calculate correctly 100 percent of the time with raw FIT (failures in time) rates as high as 10 23 , while computing correctly 98 percent of the time when experiencing raw FIT rates in excess of 10 24 , which is twenty orders of magnitude higher than the FIT rates of contemporary CMOS device technologies. We achieve this error correction with an area overhead on the order of 9x, which is quite reasonable given the high integration densities expected with nanodevices.