Hardware Description Language Design Of Σ-Δ Fractional-N Phase-Locked Loop For Wireless Applications

Ahmed El Oualkadi, Abdellah Ait Ouahman
2009 Zenodo  
This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The
more » ... d results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.
doi:10.5281/zenodo.1080399 fatcat:dqyvgow74vgc3pivd5kjhto2eu