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Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation
2000
Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00
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Comparisons among different dual-V T design choices for a large on-chip cache with single-ended sensing show that the design using a dual-V T cell and low-V T peripheral circuits is the best, and provides 10% performance gain with 1.2x larger active leakage power, and 1.6% larger cell area compared to the best design using high-V T cells.
doi:10.1145/344166.344182
fatcat:6q4z7aw36nfqpcusoej3rw4xe4