Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

Y.E. Krasteva, E. de la Torre, T. Riesgo
2008 2008 34th Annual Conference of IEEE Industrial Electronics  
The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs. Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration. The paper includes a brief description of all the building elements of the emulation framework and a use case that demonstrates the advantages of the designed pRTRs.
doi:10.1109/iecon.2008.4758347 fatcat:pljvonyew5ed7fd7pqvuxugfbu