Recording Synthesis History for Sequential Verification

Alan Mishchenko, Robert Brayton
2008 2008 Formal Methods in Computer-Aided Design  
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimizations are not applied because they are hard to verify. This paper develops a methodology for sequential equivalence checking using feedback from synthesis. A format for recording synthesis information is proposed. An implementation is described and experimentally compared against an efficient general-purpose sequential
more » ... valence checker that does not use synthesis information. Experimental results confirm expected substantial savings in runtime of equivalence checking for large designs.
doi:10.1109/fmcad.2008.ecp.8 dblp:conf/fmcad/MishchenkoB08 fatcat:imfvcobnajdcdmrmb7oipepfle