Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic

Chulwoo Kim, Seong-OoK Jung, Kwang-Hyun Baek, Sung-Mo Kang
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)  
In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias e ect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speedenhanced skewed static logic renders straightforward logic synthesis without area penalty due to
more » ... penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25 m CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed(CD)-domino by 15-27% and power delay b y 20-37%.
doi:10.1109/iscas.2000.857206 dblp:conf/iscas/KimJBK00 fatcat:6r5kmnpgojeelcafrlkaolj6ki