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In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias e ect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speedenhanced skewed static logic renders straightforward logic synthesis without area penalty due todoi:10.1109/iscas.2000.857206 dblp:conf/iscas/KimJBK00 fatcat:6r5kmnpgojeelcafrlkaolj6ki