A clock distribution network for microprocessors

P.J. Restle, T.G. McNamara, D.A. Webber, P.J. Camporese, K.F. Eng, K.A. Jenkins, D.H. Allen, M.J. Rohn, M.P. Quaranta, D.W. Boerstler, C.J. Alpert, C.A. Carter (+4 others)
2001 IEEE Journal of Solid-State Circuits  
A global clock distribution strategy used on several microprocessor chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50 000 resistors, capacitors,
more » ... inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large microprocessor chips has been measured. in 1986, where he worked on CMOS parametric testing and modeling, CMOS oxide-trap noise, package testing, and DRAM variable retention time. Since 1993, he has concentrated on tools and designs for VLSI clock distribution networks contributing to IBM's servers and high-performance ASIC designs. He holds four patents, has written 15 papers, and has given several invited talks and tutorials on high-frequency on-chip interconnects. Dr. Restle received IBM awards for the S/390 G4 and G5 microprocessors in 1997 and 1998, and for the invention of a high-performance VLSI clock distribution design methodology in 2000. Timothy G. McNamara received the B.E. degree in electrical engineering from the State University of New York, Stony Brook, in 1983 and the M.S. degree in computer engineering from Syracuse University, Syracuse, NY, in 1990. Since joining IBM in 1983, he has designed high performance clock systems for IBM's large bipolar mainframes and CMOS servers. He is currently a Senior Engineer in S/390 Custom Microprocessor Design. He currently holds eight U.S. patents and has authored or co-authored a number of technical papers. from the University of Illinois, Urbana, in 1981 and 1983, respectively. He joined IBM in 1983 in Hopewell Junction, NY, working on the design of automated test equipment. Since 1993, he has been working on circuits, clocking and integration for S/390 CMOS microprocessors. He is currently an Advisory Engineer in IBM S/390 Microprocessor Development. Peter J. Camporese received the B.S. degree in electrical engineering from the Polytechnic Institute of New York, Brooklyn, NY, in 1988 and the M.S. degree in computer engineering from Syracuse University, Syracuse, NY, in 1991. He joined the IBM Data Systems Division, Poughkeepsie, NY, in 1988, where he has worked on system performance, circuit design, physical design, and chip integration. He is currently a Senior Engineer in the IBM Server Division and a Technical Leader for the physical design and integration of CMOS zSeries microprocessors. He holds ten U.S. patents and is coauthor of several papers on high-speed microprocessor design. Cooper Union, New York, in 1978. Kwok F. Eng received the B.S.E.E. degree from The After a year of study for the M.S.E.E. degree, he joined IBM, Kingston, NY, in 1979, where he has worked on device characterization, circuit design, physical design, chip design, and EDA tools. He is currently an Advisory Engineer in charge of physical design tools for the z-series chip design group for IBM, Poughkeepsie, NY. Keith A. Jenkins (SM'98) received the Ph.D. degree in physics from Columbia University, New York, NY, for experimental work in high-energy physics. He is currently a Senior Engineer at the IBM Thomas J. Watson Research Center, where he is a member of the Communications Technology department. At the IBM Research Division, he has done research in a variety of device and circuit subjects, including high-frequency measurement techniques, electron-beam circuit testing, radiation-device interactions, low-temperature electronics, and SOI technology. His current activities include evaluation of the performance of VLSI circuits and phase-locked loops and investigations into substrate coupling in mixed-signal and RF circuits. David H. Allen received the B.S. degree in electrical engineering from the University of Kansas, Lawrence, in 1980, and is currently working toward the Master of Computer Engineering degree at the University of Minnesota, Minneapolis. He was involved in the design of high-speed memory, logic, and custom circuits at Micron Technology, Boise, ID, VTC, Bloomington, MN, and Intel, Portland, OR, before joining IBM's Enterprise Server Group, Rochester, MN, in 1992. Since then, he has developed custom 64-b PowerPC processors for AS/400 and RS/6000 servers, and has been involved in developing custom circuit techniques, clocking and latch design, and processor Charles J. Alpert
doi:10.1109/4.918917 fatcat:c2564ix42rcfxo5bez7xqupoqe