Modular Real-Time Face Detection System

Kaiyu Wang, Zhiming Song, Menglin Sheng, Ping He, Zhenan Tang
2015 Annals of Data Science  
In this paper, a novel system architecture of face detection in possession of modular characteristic is proposed, and the corresponding face detection method is described, to match with the proposed architecture. First of all, the proposed architecture of face detection consists of two modules, namely, the coprocessor module of face detection based on FPGA and target system module, which hopes to implement finial face detection, based on general purpose CPU, and USB bus is used as the
more » ... ion bridge between the two modules. Secondly, taking the characteristics of FPGA and general purpose CPU into consideration, face detection algorithm can be divided into two layers. The first layer of face detection algorithm based on skin color and eyes' graylevel variation is implemented in the FPGA, and then the corresponding detection results and image are transmitted to the second module by USB bus so as to further detect face using the algorithm combining principle component analysis with support vector machine, which is referred to as the second layer of algorithm. Because the second layer of the algorithms are operations of float-point and loop, it implemented in the general purpose CPU. This architecture enables face detection to be implemented not only in high performance computing platform in possession of USB bus interface, but also in small terminal products and low-end embedded systems, where the performance of processor and the resource of hardware are limited. Actual testing results show that the proposed system architecture can implement real-time face detection for the images with 640 × 480 resolution, and the detection accuracy is about 89 %. Keywords Modular face detection system · FPGA · The face detection based on SVM of signal pass connected components' ' Pixel counter Out_Data[6:0] IN_Data[6:0] WR_en Address[9:0] Label[0][640] Out_Data[6:0] IN_Data[6:0] WR_en Address[9:0] Label[1][640] WR_en Address IN_Data Out_Data Out_Data[6:0] IN_Data[6:0] WR_en Address[9:0] Label_1[0][640] Out_Data[6:0] IN_Data[6:0] WR_en Address[9:0] Label_1[1][640] WR_en IN_Data Out_Data Address MUX Equal_table[100]
doi:10.1007/s40745-015-0064-6 fatcat:g5rrvgzexnfwxlq6hkefvexbxi