Efficient algorithms for verifying memory consistency

Chaiyasit Manovit, Sudheendra Hangal
2005 Proceedings of the 17th annual ACM symposium on Parallelism in algorithms and architectures - SPAA'05  
One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement. It has been shown in prior work, however, that accurately verifying such compliance even of a single execution result is an NP-complete problem, for an unlimited number of processors. In this paper, we present a suite of post-mortem algorithms that perform the compliance check in an efficient, although not exhaustive,
more » ... . Our algorithms employ the concept of vector clocks together with a heuristic made from a variation of the problem in P class. An implementation of these algorithms has been successful in efficiently detecting several bugs during the course of validating the design of commercial microprocessors and systems. Although our algorithms are presented with the Total Store Order (TSO) memory model, the ideas can also be applied to other models ranging from Sequential Consistency (SC) to a more relaxed one such as Relaxed Memory Order (RMO).
doi:10.1145/1073970.1074011 dblp:conf/spaa/ManovitH05 fatcat:7ks4xzcrwvalfo3scljn57yblq