Automatic verilog code generation through grammatical evolution

Ulya R. Karpuzcu
2005 Proceedings of the 2005 workshops on Genetic and evolutionary computation - GECCO '05  
This work aims to investigate the automatic generation of Verilog code, representing digital circuits through Grammatical Evolution (GE). Preliminary tests using a simple full adder generation problem have been performed.
doi:10.1145/1102256.1102346 dblp:conf/gecco/Karpuzcu05 fatcat:frc77fohwnfddk6or73spaxz54