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Multi-level Unified Caches for Probabilistically Time Analysable Real-Time Systems
2013
2013 IEEE 34th Real-Time Systems Symposium
Caches are key resources in high-end processor architectures to increase performance. In fact, most highperformance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, cache hierarchies severely challenge the computation of tight worstcase execution time (WCET) estimates. On the one hand, the analysis of the timing behaviour of a single level of cache is already challenging, particularly for data accesses. On the other hand, unifying data
doi:10.1109/rtss.2013.43
dblp:conf/rtss/KosmidisAQC13
fatcat:6nxuac3owfculhavh5p32ye4fm