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An implementation of memory-based on-chip analogue test signal generation
2003
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC
This paper presents a memory-based on-chip analogue test signal generation approach that is suitable for the test of an Analogue and Mixed-Signal (AMS) core. This core contains programmable electronic interfaces for acoustic and ultrasound transducers. The test signals that must be generated on-chip have only low or moderate frequencies (10 Hz-10 MHz). The test circuitry designed in a 0.18 µ µm CMOS technology includes a programmable shift-register, a clock divider, and a programmable
doi:10.1145/1119772.1119921
dblp:conf/aspdac/MirRDR03
fatcat:aoz22rfmoveydoo2vffebtsqty