2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator

S. Tontisirin, R. Tielert
2006 Advances in Radio Science  
<p><strong>Abstract.</strong> A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with
more » ... rator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18 μm CMOS technology. It has an active area of 0.7 mm<sup>2</sup> and consumes 100 mW at 1.8 V supply. The CDR has low jitter operation in a wide frequency range from 1&amp;ndash;2.25 Gb/s. Measurement of Bit-Error Rate is less than 10<sup>&amp;minus;12</sup> for 2.25 Gb/s incoming data 2<sup>7</sup>&amp;minus;1 PRBS, jitter peak-to-peak of 0.7 unit interval (UI) modulation at 10 MHz.</p>
doi:10.5194/ars-4-287-2006 fatcat:hlpsrp2mqnc5pdh2crpebi5oji