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As complexity of embedded system increases, configurable hardware is becoming more attractive because it provides a fast and efficient basis for design development. As a consequence, one of the most promising embedded architecture consists in the replication of Processing Elements (PEs) connected through a Network-on-Chip (NoC). Such architectures provide computation parallelism, scalability, and reduced design time thanks to reusability. This paper describes the development of a scalable,doi:10.1109/reconfig.2011.66 dblp:conf/reconfig/BusseuilBAOBSBRT11 fatcat:qcj7mvj43rhwniavjnlbcxrfye