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Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor
2005
IEEE transactions on computers
Low-power embedded processors utilize compact instruction encodings to achieve small code size. Such encodings place tight restrictions on the number of bits available to encode operand specifiers and, thus, on the number of architected registers. As a result, performance and power are often sacrificed as the burden of operand supply is shifted from the register file to the memory due to the limited number of registers. In this paper, we investigate the use of a windowed register file to
doi:10.1109/tc.2005.132
fatcat:ow4igm53l5h45lyj3osm7thrma