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A novel framework for logic verification in a synthesis environment
1996
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Absbact-A new methodology for formal logic vedication of combinational circuits is presented. Specifically, a structural (logic network) approach is used, based on indirect implications derived by recursive learning. It is shown that implications can be used to capture similarity between designs. This is extended to formulate a hybrid approach, this structural (logic network) information is used to reduce the complexity of a subsequent functional method based on OBDD's. We demonstrate that
doi:10.1109/43.486269
fatcat:7j2taznitbevdce6f74nuu44qa