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Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations
[chapter]
2006
Lecture Notes in Computer Science
This article starts with a discussion of three different attacks on masked AES hardware implementations. This discussion leads to the conclusion that glitches in masked circuits pose the biggest threat to masked hardware implementations in practice. Motivated by this fact, we pinpointed which parts of masked AES S-boxes cause the glitches that lead to side-channel leakage. The analysis reveals that these glitches are caused by the switching characteristics of XOR gates in masked multipliers.
doi:10.1007/11894063_7
fatcat:qzakzmwjfzbwvmlpscu5vgznii