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This paper proposes a schedule synthesis approach taking fault diagnosis and testability into account at design time. Over the last years, the amount of automotive software and hardware has been successively growing. As a consequence, the complexity of present-day Electrical and Electronic (E/E) architectures reached a state where current fault detection mechanisms are often not sufficient or computationally too expensive to guarantee a reliable system functionality. As a remedy, we propose adoi:10.1109/isicir.2014.7029550 dblp:conf/isicir/WaszeckiSLC14 fatcat:datm5x7trvae7b5rdj6yap6e4i