A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is
Thermo-elastic strain is induced by through silicon vias (TSV) due to the difference of thermal expansion coefficients between the copper (∼18 ppm/•C) and silicon (∼2.8 ppm/•C) when the structure is exposed to a thermal budget in the three dimensional integrated circuit (3DIC) process. These thermal expansion stresses are high enough to induce the delamination on the interfaces between the copper, silicon, and isolated dielectric. A compact analytic model for the strain field induced bydoi:10.5875/ausmt.v5i2.323 fatcat:72uahvfrgvb4pdxsma5oitnotm