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Using unsatisfiable cores to debug multiple design errors
2008
Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported quite well using simulation or formal verification. But locating the fault site is typically a time consuming manual task. Techniques to automate debugging and diagnosis have been proposed. Approaches based on Boolean Satisfiability (SAT) have been demonstrated to be very effective. In this work debugging on the gate level is
doi:10.1145/1366110.1366131
dblp:conf/glvlsi/SulflowFBD08
fatcat:aoi4zb7nzbcajggstdoosy5lai