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Improving cache performance using read-write partitioning
2014
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Cache read misses stall the processor if there are no independent instructions to execute. In contrast, most cache write misses are off the critical path of execution, since writes can be buffered in the cache or the store buffer. With few exceptions, cache lines that serve loads are more critical for performance than cache lines that serve only stores. Unfortunately, traditional cache management mechanisms do not take into account this disparity between read-write criticality. This paper
doi:10.1109/hpca.2014.6835954
dblp:conf/hpca/KhanAWMJ14
fatcat:rbonj4nuybbjvgejy5jbn5ntsi