Application-Specific Heterogeneous Network-on-Chip Design

D. Demirbas, I. Akturk, O. Ozturk, U. Gudukbay
2013 Computer journal  
NoC design is to find the right balance among different tradeoffs, such as communication latency, power consumption and chip area. We propose a novel approach that generates latency-aware heterogeneous NoC topology. Experimental results show that our approach improves the total communication latency up to 27% with modest power consumption.
doi:10.1093/comjnl/bxt011 fatcat:45deduktujfm7bvqh3pdcbaqt4