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This paper addresses on three different architectures of digital decimation filter design of a multi-standard RF transceivers. Instead of using single stage decimation filter network, the filters are implemented in multiple stages using FPGA to optimize the area, delay and dynamic power consumption. The proposed decimation filter architectures reflect the considerable reduction in area and dynamic power consumption without degradation of performance. The filter coefficients are derived fromdoi:10.15676/ijeei.2015.7.3.13 fatcat:rlznw4m3rnb2tjnco3wgs3ieki