Delay defect screening for a 2.16GHz SPARC64 microprocessor

Noriyuki Ito, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara (+3 others)
<span title="">2006</span> <i title="ACM Press"> Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC &#39;06 </i> &nbsp;
This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A nonrobust delay test is used while each test vector is compacted to detect multiple transition faults in a standard scan-based design targeting a stuck-at fault test. Our test technique applied to a microprocessor designed with 6M gate logic, 4MB level 2 cache, and 239K latches, achieves 90% coverage using 3,103 test vectors. We estimate the distribution of the delay of paths covered
more &raquo; ... y our delay test. We also show the effectiveness of our method by discussing the correlation between the screening result and the actual number of delay defects.
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