Design of an Efficient Fault and Congestion Free NoC Design using Adaptive Routing on FPGA
International journal of recent technology and engineering
Manufacturing fault-free System on Chips (SoCs) with performance scaling is a challenging task. The Network on Chip (NoC) architecture offers scalability and reliability to the SoC designs. In this paper, the fault detection and correction mechanism for a congestion-free Router architecture along with Mesh-NoC for different sizes are discussed. The proposed hardware architecture of NoC-Router includes Input registers (which store five -port inputs with Fault injection), Error Correction Code
... Correction Code (that encodes the input data) followed by packet formation with Arbitration mechanism (that grants the permission to priority based encoder). The prior packet data is input to the adaptive-XY routing and it operates with the various congestion issues on choosing the shortest route. The detection and correction of the faulty bits from the network are monitored by ECC decoder. This NoC router can tolerate transient fault; provides low-latency and high throughput performance for all MPSoC applications. The Normal –XY Routing algorithm is incorporated in same router for comparison purpose. The synthesis results includes chip area, and maximum operating frequency over Artix-7 FPGA technology. Outcomes are tabulated and they show a marked improvement over previous cases. The performance evaluation is considered in terms of average latency and maximum throughput at different input traffic. It's analyzed for novelty features as well.