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This paper presents the design of an asymmetrical Doherty power amplifier (DPA) with improved linearity and efficiency performance. Resonator-type drain bias networks, providing high impedances at the carrier frequency and low impedances with small variation at the envelope frequency, are introduced to reduce the DPA's memory effects when transmitting wideband signals. The general criteria for DPA design are summarized, and the approach to obtain optimum fundamental and harmonic impedances isdoi:10.2528/pierc15013002 fatcat:cbdawy6sg5gf3mc4qy5mpwxpem