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An architecture for high-performance scalar computation is proposed and discussed. The main feature of the architecture is a high degree of decoupling between operand access and execution. This results in an implementation that has two separate instruction streams that communicate via architectural queues. Performance comparisons with a conventional scalar architecture are given, and these show that significant performance gains can be realized. Single-instruction-stream versions, both physicaldoi:10.1145/285930.285982 dblp:conf/isca/Smith98d fatcat:rerg34mrpjecpe32m74foppnwm