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Exploiting Symmetrization and D-reducibility for Approximate Logic Synthesis
2020
IEEE transactions on computers
Approximate synthesis is a recent trend in logic synthesis where one changes some outputs of a logic specification, within the error tolerance of a given application, to reduce the complexity of the final implementation. We attack the problem by exploiting the allowed flexibility in order to maximize the regularity of the specified Boolean functions. Specifically, we consider two types of regularity: symmetry and D-reducibility, and contribute two algorithms to find, respectively, a symmetric
doi:10.1109/tc.2020.3043476
fatcat:ltyoo3qex5gkpc5x7stadkm354