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Architectural Power Estimation Based on Behavior Level Profiling
1998
VLSI design (Print)
High level synthesis is the process of generating register transfer (RT) level designs from behavioral specifications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems [1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it is possible to accurately estimate the power consumption of RT level designs, then a low power
doi:10.1155/1998/93106
fatcat:dbj3fnjmjncxvh4uli5dm56niu